Not applicable.
Not applicable.
The present invention relates to PET scanners generally and specifically to a method and apparatus for increasing the counting efficiency of a digital time stamping PET scanner by eliminating counting error due to the xe2x80x9cpicket fencexe2x80x9d effect.
Positrons are positively charged electrons which are emitted by radionuclides which have been prepared using a cyclotron or other device. The radionuclides most often employed in diagnostic imaging are fluorine-18, carbon-11, nitrogen-13 and oxygen-15. Radionuclides are employed as radioactive tracers called xe2x80x9cradiopharmaceuticalsxe2x80x9d by incorporating them into substances such as glucose or carbon dioxide. One common use for radiopharmaceuticals is in the medical imaging field.
To use a radiopharmaceutical in imaging, the radiopharmaceutical is injected into a patient and accumulates in an organ, vessel or the like, which is to be imaged. It is known that specific radiopharmaceuticals become concentrated within certain organs or, in the case of a vessel, that specific radiopharmeceuticals will not be absorbed by a vessel wall. The process of concentrating often involves processes such as glucose metabolism, fatty acid metabolism and protein synthesis. Hereinafter, in the interest of simplifying this explanation, an organ to be imaged will be referred to generally as an xe2x80x9corgan of interestxe2x80x9d and prior art and the invention will be described with respect to a hypothetical organ of interest. After a radiopharmaceutical becomes concentrated within an organ of interest and while the radionuclides decay, the radionuclides emit positrons. The positrons travel a very short distance before they encounter an electron and, when the positron encounters an electron, the positron is annihilated and converted into two photons, or gamma rays. This annihilation event is characterized by two features which are pertinent to medical imaging and particularly to medical imaging using photon emission tomography (PET). First, each gamma ray has an energy of essentially 511 keV upon annihilation. Second, the two gamma rays are directed in substantially opposite directions.
In PET imaging, if the general locations of annihilations can be identified in three dimensions, the shape of an organ of interest can be reconstructed for observation. To detect annihilation locations, a PET scanner is employed. An exemplary PET scanner includes a plurality of detector modules and a processor which, among other things, includes coincidence detection circuitry. An exemplary detector module includes six adjacent detector units. An exemplary detector unit includes an array of crystals (e.g. 36) and a plurality of photo-multiplier tubes (PMTs). The crystal array is located adjacent to the PMT detecting surfaces. When a photon impacts a crystal, the crystal generates light which is detected by the PMTs. The PMT signal intensities are combined and the combined signal is compared to a threshold energy level (e.g. 100 keV). When the combined signal is above the threshold, an event detection pulse (EDP) is generated which is provided to the processor coincidence circuitry. Other hardware determines which crystal generated the light (i.e. absorbed the photon).
The coincidence circuitry identifies essentially simultaneous EDP pairs which correspond to crystals which are generally on opposite sides of the imaging area. Thus, simultaneous pulse pair indicates that an annihilation has occurred on a straight line between an associated pair of crystals. Over an acquisition period of a few minutes, millions of annihilations are recorded, each annihilation associated with a unique crystal pair. After an acquisition period, recorded annihilation data is used via any of several different well known procedures to construct a three dimensional image of the organ of interest.
A PET scanner may test the energy level before or after testing for coincidence timing and the coincidence timing test may be either analog or digital. In a typical analog coincidence circuit the duration of a timing signal is set to a pre-determined value (e.g. W/2 where W is a time period corresponding to a coincidence window). The timing signals from the detector units are then combined using conventional AND logic gate which produces an output only when two timing pulses overlap (i.e. two consecutive pulses are within +/xe2x88x92W/2).
In a typical digital coincidence circuit each EDP timing signal is compared to a master clock signal in a time to digital converter (TDC) and a time stamp digital value is provided for the EDP. The time stamp digital value from the TDC corresponds to the time lapsed between the previous master clock pulse and the EDP. For instance, in one exemplary system a master clock cycle may be 250 nanoseconds and the TDC may be capable of further dividing each master cycle into 192 separate sub-periods. For the purposes of this explanation a master clock cycle of 250 nanoseconds and further division of each cycle into 192 time stamps will be assumed although other cycle divisions and stamp divisions are completed. After each master clock cycle the time stamps corresponding to all EDPs detected during the completed master clock cycle (i.e. the stamps which occurred between the preceding two master clock pulses) are compared. EDPs which have time stamp differences between the time stamps of smaller than +/xe2x88x92W/2 are identified as coincidence pairs.
During an acquisition period there are several sources of annihilation detection error. One source of error in systems that include digital coincidence circuitry is referred to as the xe2x80x9cpicket fence effectxe2x80x9d. To this end, as indicated above, event detection pulses are generated relative to a master clock cycle and thereafter all time stamps corresponding to pulses that occurred during the master clock cycle are compared to identify coincidence pairs. In this type of system, EDPs that occur either near the beginning or the end of a master clock cycle may have a matching coincidence event that falls into either a previous or a subsequent master clock cycle. Coincidence pairs including EDPs that xe2x80x9cstraddlexe2x80x9d two master clock cycles are effectively lost as the coincidence circuitry has no way to associate the two EDPs with a single annihilation event. In some cases event losses due to the picket fence effect have accounted for as much as 1% of the total possible signal. The amount of loss depends on the width of the event time stamp and period of the master clock cycle. In the case of wide time stamp and short clock cycle, this loss can be several percent.
The picket fence phenomenon can best be understood by example and, to this end, refer to FIG. 4 where a timing diagram 98 illustrates the end and the beginning of consecutive leading and following master clock cycles, respectively, along with exemplary EDPs. The end of the leading cycle as illustrated includes time stamps 186 through 191 while the beginning of the following cycle includes time stamps 0 through 5. The EDPs that have time stamps during the leading cycle are identified by downwardly directed arrows while the EDPs that have time stamps during the following cycle are identified by upwardly directed arrows. Six exemplary EDPs 1l, 21, 3l, 4l, 5l and 6l are illustrated with EDPs 1l, 2l and 3l occurring during the leading clock cycle and having time stamps 186, 188 and 190, respectively, while EDPs 4l, 5l and 6l occur during the following clock cycle and having time stamps 0, 2 and 5.
For this example, assume that the EDPs 1l, 2l, 3l, 4l, 5l and 6l correspond to three separate annihilation events. In addition, assume a coincidence window W period corresponding to 12 consecutive time stamps. In this case, half the coincidence window (i.e., W/2) corresponds to six time stamp periods and therefore, any two EDPs having time stamps within 6 time stamp periods of each other should be considered for coincidence pairing.
Thus, referring still to FIG. 4, while EDPs 1l, 2l, 3l, 4l, 5l and 6l correspond to three separate annihilation events, potential coincidence pairs may include EDPs 1l and 2l (i.e., EDPs 1l and 2l may correspond to a single event), EDPs 2l and 3l, EDPs 3l and 4l, EDPs 4l and 5l, EDPs 5l and 6l, EDPs 1l and 3l, EDPs 1l and 4l, EDPs 2l and 4l, EDPs 2l and 5l, EDPs 3l and 4l, EDPs 3l and 5l and EDPs 4l and 6l. Nevertheless, exemplary coincidence detection circuitry would fail to recognize many of the potential coincidence pairings because the circuitry would not compare EDP time stamps between the leading and following cycles. Specifically, in this example, in the leading cycle, the coincidence circuitry would consider pairing EDPs 1l and 2l, 2l and 3l and 1l and 3l, while in the following cycle the circuitry would consider pairing EDPs 4l and 5l, 4l and 6l and 5l and 6l. The circuitry would ignore possible EDP pairings 2l and 4l, 2l and 5l, 3l and 4l, and 3l and 5l. Thus, assuming that, based on other signal characteristics (e.g., angles between crystals that generate EDPs, etc.), the coincidence circuitry identifies coincidence pairs including EDPs 1l and EDPs 2l and 5l and 6l (xe2x80x9cfound and acceptedxe2x80x9d pairs as illustrated), the circuitry would miss the potential pair including EDPs 3l and 4l (xe2x80x9cmissed, no matchxe2x80x9d as illustrated).
One way to eliminate this dual clock period loss of events is to acquire data in a list mode during acquisition, store the acquired data and subsequently process the data to identify coincidence events. This solution, while ideal, is impractical with existing systems as the computational and archiving overhead would be excessive.
Another way to avoid picket fence related loss of events would be to repeat the coincidence comparison for clock cycles that are shifted so that they include the time stamps at both the end of one xe2x80x9cnormalxe2x80x9d cycle and the beginning of another cycle. In this case, coincidence pairs having EDPs in consecutive normal clock cycles would be detected and counted. While theoretically feasible, this solution, unfortunately, would require a second complete comparison circuit which would be far too expensive for most applications.
Faced with the aforementioned problems and the realization that picket fence related losses are relatively minimal (e.g., 1% of the total possible signal level), the industry has generally accepted picket fence effect losses. Nevertheless, as other system parameters and performance have been improved, newer systems have adopted or will be adopting master clocks that have shorter master clock cycles. Because the picket fence effect loss occurs at the end of every master clock cycle, the picket fence related error is inversely proportional to the master clock period such that shorter clock cycles cause greater error (e.g., an error  greater than 1% of the total signal). Thus, the picket fence effect error will be increasing and, at least for some applications, may be at unacceptable levels.
An exemplary embodiment of the invention includes a method for reducing event loss in a digital time stamped PET scanner including a master clock that has a master clock cycle and an event processing circuit that divides each clock cycle into a plurality of time stamps. The scanner also including coincidence detection circuitry that compares time stamps within each clock cycle to identify coincidence event pairs. The method comprises the steps of, for consecutive leading and following clock cycles where each of the leading and following cycles are master cycles, identifying an overlap period that includes a portion of a first of the master cycles adjacent a second of the master cycles, adding the overlap period to the second of the master cycles to generate an extended cycle, identifying overlap events that occur during the overlap period in the first of the master cycles, copying the overlap events to the overlap period in the extended cycle, comparing events in the extended cycle to identify coincidence event pairs and counting the event pairs.
In at least some embodiments the step of comparing includes, for each coincidence event pair, determining if both events in the pair occur during the overlap period and, where both events occur during the overlap period, skipping the step of counting the event pair. In some embodiments the leading cycle and following cycle are the first and second cycles, respectively, so that the step of identifying an overlap period includes the step of identifying the ending portion of the leading cycle adjacent the following cycle. In other embodiments the leading cycle and following cycle are the second and first cycles, respectively, so that the step of identifying an overlap period includes the step of identifying the beginning portion of the following cycle adjacent the leading cycle.
In some embodiments the scanner is characterized by a coincidence window and the overlap period has a duration at least as long as one half the coincidence window.
In addition to the method, the invention includes other similar methods and also contemplates an apparatus that includes either dedicated hardware or that may be implemented in software as computer programs that represent algorithms for execution by a conventional-type digital processor adapted for imaging applications.
These and other aspects of the invention will become apparent from the following description. In the description, reference is made to the accompanying drawings which form a part hereof, and in which there is shown a preferred embodiment of the invention. Such embodiment does not necessarily represent the full scope of the invention and reference is made therefore, to the claims herein for interpreting the scope of the invention.